1. Field of the Invention
The present invention relates to a signal transmission circuit that is favorably used in shift registers that drive solid-state imaging apparatuses, liquid crystal displays, memory devices, and the like.
Priority is claimed on Japanese Patent Application No. 2004-043565, filed Feb. 19, 2004, the contents of which are incorporated herein by reference.
2. Description of Prior Art
FIG. 11 shows a portion of a signal transmission circuit that is disclosed in Japanese Patent Application Publication (JP-B) No. 3-75960 as an example of a conventional signal transmission circuit that is composed solely of NMOS transistors.
As is shown in FIG. 11, an input line φST is connected to a gate of a MOS transistor M2 via a MOS transistor M1, and to a ground line GND via a MOS transistor M3. A bootstrap capacitor C1 is connected between the gate and source of the MOS transistor M2, and the source of the MOS transistor M2 is connected to a gate of a MOS transistor M52 via a MOS transistor M51.
The source of the MOS transistor M2 is connected to the ground line GND via a MOS transistor M4 and a MOS transistor M53. A bootstrap capacitor C51 is connected between the gate and source of the MOS transistor M52. The source of the MOS transistor M52 is connected to the ground line GND via a MOS transistor M14, and the source of the MOS transistor M52 is connected to the subsequent circuit.
A clock line φ1 is connected to the gate of the transistors M1 and M4 and to the drain of the transistor M52, and a clock line φ2 is connected to the gate of the transistors M51 and M14 and to the drain of the transistor M2. Thereafter, these transistor and bootstrap capacitor circuits are repeatedly connected in sequence. In addition, OUT1, OUT2 . . . are output lines, G2, G52 . . . are gate lines of the transistors M2 and M52, Cs1 is a parasitic capacitor that does not contribute to the bootstrap effect that is applied to G2, G52 . . . , CDG is a capacitor between a drain and a gate, and CL is an output capacitor.
FIG. 12 is a timing chart for schematically describing an operation of the signal transmission circuit shown in FIG. 11. The signals shown by φ1, φ2, and φST in FIG. 12 are applied respectively to the clock lines φ1 and φ2 and to the input line φST in the circuit shown in FIG. 11, and, in FIG. 11, GND is a ground potential. Here, potentials of high level of the input signal φST and the clock signals φ1 and φ2 are defined as VH, and potential of all threshold values of the MOS transistors are defined as Vth.
In FIG. 12, firstly, when the input signal φST and the clock signal φ1 change to a high level, the transistor M1 is in a conducting state. Consequently, the high level of the input signal φST is sent to the transistor M1, and charge is accumulated in the bootstrap capacitor C1. As a result, as is shown by VG2 in FIG. 12, the potential of the gate line G2 of the transistor M2 changes to a high level. At this time, if potential of the gate line G2 of the transistor M2 is taken as VH′, the Formula 1 below applies.VH′=VH−Vth  (Formula 1)
When the potential VG2 of the gate line G2 of the transistor M2 changes to a high level, the transistor M2 is in a conducting state. As a result, as is shown by VOUT1 in FIG. 12, a low level of the clock signal φ2 is output to the output line OUT1.
Next, when the clock signal φ2 changes to a high level, the potential VG2 of the gate line G2 of the transistor M2 rises by Formula 2 via the bootstrap capacitor C1.
CS1 is a parasitic capacitor that does not contribute to the bootstrap effect and that is caused by the gate of the transistor M2.
As a result, the potential VG2 of the gate line G2 of the transistor M2 changes to Formula 3, and, at this time, if the relationship shown in Formula 4 applies, the high level of the clock signal φ2 is extracted to the source of the transistor M2.VA={C1/(C1+CS1)}VH  (Formula 2)VG2=VH′+{C1/(C1+CS1)}VH  (Formula 3)VG2−Vth≧VH  (Formula 4)
Accordingly, as is shown by the VOUT1 in FIG. 12, the high level is extracted to the output line OUT1. At this time, simultaneously, in synchronization with the clock signal φ2, the transistor M51 is placed in a conducting state. As a result, because a load is accumulated in the bootstrap capacitor C51, the potential of the gate line G52 of the transistor M52 changes to a high level, as is shown by the VG52 in FIG. 12.
Next, when the clock signal φ1 once again changes to a high level, the potential VG52 of the gate line 52 of the transistor M52 is lifted to a higher voltage than the high level potential VH of the clock signal φ1 via the bootstrap capacitor C51. As a result, the high level of the clock signal φ1 is extracted to the source of the transistor M52, and the high level is extracted to the output line OUT2, as is shown by the VOUT2 in FIG. 12.
In the same way, the potentials of the gate line G102 and the output line OUT3, and the potentials of the gate line 152 and the output line OUT4 that are shown in FIG. 11 change respectively in the manners shown by VG102, VOUT3, VG152, and VOUT4 shown in FIG. 12. Accordingly, in this circuit, high level of the input signal φST are sequentially transmitted, and the high level is extracted in sequence to the output lines OUT1, OUT2, OUT3, and OUT4.
FIG. 13 is a portion of a signal transmission circuit disclosed in Japanese Patent Application Publication (JP-B) No. 5-84967 as an example of a conventional signal transmission circuit that is composed solely of NMOS transistors.
An input line φST is connected to a gate of the MOS transistor M2 and to the gate of the MOS transistor M12 via the MOS transistor M1, and the bootstrap capacitor C1 is connected between the gate and source of the MOS transistor M2.
The source of the MOS transistor M2 is connected to the gate of the MOS transistor M52 and to the gate of a MOS transistor M62 via a MOS transistor M51. The source of the MOS transistor M2 is also connected to a ground line GND via a MOS transistor M13, and the bootstrap capacitor C51 is connected between the gate and source of the MOS transistor M52.
The source of the MOS transistor M52 is connected to the ground line GND via a MOS transistor M63, and the source of the MOS transistor M52 is connected to the next circuit. Furthermore, a clock line φ1 is connected to the gates of the MOS transistors M1 and M11, and to the drain of the MOS transistor M52. A clock line φ2 is connected to the gates of the MOS transistors M51 and M61, and to the drain of the MOS transistor M2.
In addition, the drains of the MOS transistors M11 and M61 are connected to a power supply line VDD, and the sources of the MOS transistors M11 and M61 are connected respectively to the gates of the transistors M13 and M63 and to the drains of the MOS transistors M12 and M62. The sources of the MOS transistors M12 and M62 are connected to the ground line GND, and, thereafter, these transistor and bootstrap capacitor circuits are repeatedly connected in sequence. Here, OUT1, OUT2 . . . are output lines, G2, G52 . . . are gate lines of the transistors M2 and M52, Cs1 is a parasitic capacitor that does not contribute to the bootstrap effect and that is applied to G2, G52 . . . , CS2 is a parasitic capacitor that does not contribute to the bootstrap effect and that is caused by the gates of the transistors M12 and M62 . . . , and 10, 60, 110, and 160 are output line fixing circuits.
Next, using timing chart shown in FIG. 14, an operation of the signal transmission circuit shown in FIG. 13 will be schematically described.
The signals shown by φ1, φ2, and φST in FIG. 14 are applied respectively to the clock lines φ1 and φ2 and to the input line φST in the circuit shown in FIG. 13, and, in FIG. 13, GND is a ground potential.
Here, potentials of high level of the input signal φST and the clock signals φ1 and φ2 are defined as VH, and all threshold values of the MOS transistors are defined as Vth.
Firstly, when the input signal φST and the clock signal φ1 change to a high level, the transistor M1 changes to a conducting state. Consequently, the high level of the input signal φST is sent to the transistor M2, and a charge is accumulated in the bootstrap capacitor C1. As a result, as is shown by VG2 in FIG. 14, the potential of the gate line G2 of the transistor M2 changes to a high level. At this time, if the potential of the gate line G2 of the transistor M2 is taken as VH′, the Formula 5 below applies.VH′=VH−Vth  (Formula 5)
When the potential VG2 of the gate line G2 of the transistor M2 changes to a high level, the transistor M2 is placed in a conducting state. As a result, as is shown by VOUT1 in FIG. 14, a low level of the clock signal φ2 is output to the potential VOUT1 of the output line OUT1. At this time, because the transistor M12 is also in a conducting state, as is shown by VG13 in FIG. 14, the potential of the gate line G13 of the transistor M13 becomes the ground potential, and the transistor M13 changes to a cutoff state.
Next, when the clock signal φ2 changes to a high level, the potential VG2 of the gate line G2 of the transistor M2 rises by Formula 6 via the bootstrap capacitor C1.
CS1 and CS2 are parasitic capacitors that do not contribute to the bootstrap effect and that is caused respectively by the gates of the transistors M2 and M12.
As a result, the potential VG2 of the gate line G2 of the transistor M2 changes to Formula 7, and if the relationship shown in Formula 8 applies, the high level of the clock signal φ2 is extracted to the source of the transistor M2. At this time, because the potential VG13 of the gate line G13 of the transistor M13 is continuously fixed to the ground potential, the transistor M13 remains fixed in the cutoff state, and is cut off from the output line OUT 1. Therefore, there are no harmful effects on the output line OUT 1. Accordingly, the high level is extracted to the output line OUT1, as is shown by VOUT1 in FIG. 14.VA={C1/(C1+CS1+CS2)}VH  (Formula 6)VG2=VH′+{C1/(C1+CS1+CS2)}VH  (Formula 7)VG2−Vth≧VH  (Formula 8)
At this time, simultaneously, in synchronization with the clock signal φ2, the transistor M51 is placed in a conducting state. As a result, because a load is accumulated in the bootstrap capacitor C51, the potential of the gate line G52 of the transistor M52 changes to a high level, as is shown by the VG52 in FIG. 14.
Next, when the clock signal φ1 once again changes to a high level, the potential VG52 of the gate line 52 of the transistor M52 is lifted to a higher potential than the high level potential VH of the clock signal φ1 via the bootstrap capacitor C51. As a result, the high level of the clock signal φ1 is extracted to the source of the transistor M52. Accordingly, the high level is extracted to the potential of the output line OUT2, as is shown by the VOUT2 in FIG. 14.
Note that, at this time, because the input signal φST is at a low level, the potential VG2 of the gate line G2 of the transistor M2 changes to a low level, and the transistor M12 changes to a cutoff state. In contrast, because the transistor M11 is in a conducting state, the potential VG13 of the gate line G13 of the transistor M13 changes to a high level. As a result, because the transistor M13 is in a conducting state, the potential VOUT1 of the output line OUT1 is fixed to the ground potential.
In the same way, the potentials of the gate line G102 of the transistor M102, the gate line G113, the output line OUT3, the gate line 152, the gate line 163 of the transistor M163, and the output line OUT 4 as are shown in FIG. 13, change respectively in the manners shown by VG102, VG113, VOUT3, VG152, VG163, and VOUT4 shown in FIG. 14.
Accordingly, in this circuit, the high level of the input signal φST are sequentially transmitted, and the high level are extracted in sequence to the output lines OUT1, OUT2, OUT3, and OUT4.